1. Field of the Invention
The present invention relates to the field of computers and computer processors, and more particularly to analog-to-digital converters (ADCs).
2. Description of the Background Art
An analog-to-digital converter (ADC) is an electronic circuit that converts continuous signals to discrete digital numbers. Typically, an ADC is an electronic device that converts an input analog voltage to a digital number.
The analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter, typically reported as the number of samples per second (sps).
A continuously varying bandlimited signal can be sampled at intervals of time T, the sampling time, and measured and stored, and then the original signal can be approximately reproduced from the discrete-time values by an interpolation formula. This reproduction achieves maximum possible accuracy only if the sampling rate is higher than twice the highest frequency of the signal, which is called the Nyquist-Shannon sampling theorem.
Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion, called the conversion time. An input circuit called a sample and hold performs this task, usually by using a capacitor to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally.
It is often desirable to be able to sample analog signals in an integrated circuit (IC) at very high frequencies, for example in the range of several gigahertz (GHz). However, certain types of ICs are made with older semiconductor manufacturing and material technology that is capable of sampling signals only at lower frequencies, for example in the range of 1-2 GHz or less. It would be desirable to utilize this older technology and still achieve very high frequency sampling rates.
FIG. 1 shows an overview of an analog-to-digital (A-to-D) sampling system 100 as is currently known in the art. Embedded in a chip 101 is an A-to-D block 102. A-to-D block 102 has a data output 105, typically a parallel bus, and a sampling frequency control 104, which is used to control sampling of the input signal 103. The highest frequency component of the input signal is designated as fi, and the sampling frequency, designated as fs must be at least twice the frequency of fi, preferably 2.2 times the frequency of fi for sampling that retains the maximum information about the original signal as possible. Therefore, if the desired input frequency fi is in the 10 GHz range, the chip must be able to clock the sampling frequency fs at approximately 20-22 GHz. Building a chip with such a high sampling frequency is more costly, and the architecture of such chips does not permit embedding of large data functions such as CPUs, memory, etc. in such a chip.
Various approaches have been taken to find an economical system that can sample high frequency input rates. In an article entitled, Design of a High-Performance Analog-to-Digital Converter, by Kevin Nary, published in CSD Magazine in October 1998, Nary discloses a folding and interpolating 8-bit 2-Gsps ADC. The number of comparators required for a 4-bit ADC is reduced from fifteen to six when switching from a flash to a folding architecture. This ADC increases the analog bandwidth and the maximum sample rate and consumes less power than a flash architecture ADC. One method of achieving a folding function uses cross-coupled, differential amplifiers, where a single fold is achieved with two cross-coupled, differential amplifiers. By adding more resistors and differential pairs, the number of folds may be increased. Nary reported results of a 2 GHz sampling frequency with 98 MHz input frequency.
Another approach has been disclosed in an article entitled, Capturing Data from Gigasample Analog-to-Digital Converters, by Ian King, published in I/O Magazine in January 2006, which discloses a method of de-multiplexing the digital output. For a 1.5 GHz sample rate, the conversion data will be output synchronous to a 750 MHz clock, where the data is presented to the outputs on both the rising and falling edges of the clock. Two latches are then used, wherein one latch is clocked on the rising edge of the phase-locked data clock and a second latch is clocked using a signal that is 180 degrees out of phase. This reduces the output to 375 MHz. After latching the incoming data, the clock domain is shifted using an intermediate set of latches so that all of the data can be clocked into a memory array on the same clock edge, which de-multiplexes the data rate to 187.5 MHz. A single-channel device can be put into a dual-edge sampling mode to increase the sampling speed from 1.5 Gsps to 3.0 Gsps, which increases the number of output data bits from 8 to 16.
A system and method are clearly needed in which much higher sampling frequencies than 2-3 GHz can be adequately sampled, which uses conventional lower cost semiconductor manufacturing and material technology.